1. Field of the Invention
The invention relates to a semiconductor memory cell, in particular a Static Random Access Memory (SRAM) memory cell, and a method for compensating for a leakage current flowing into the SRAM memory cell.
2. Description of the Related Art
Semiconductor memory cells such as static memory cells (e.g., SRAM memory cells), by way of example, are used in many instances in integrated circuits. SRAMs are fabricated as individual modules and also integrated in addition to other components on a chip. The proportion of area taken up by SRAMs in microprocessors and in other highly complex logic circuits is up to 50%. Therefore, a careful design of the SRAM and of the peripheral circuits is of great importance in many applications. An SRAM is a read-write memory with random access. The term static memory is employed since the information written in electrically can be stored without limitation as long as the supply voltage is not turned off. A known SRAM memory cell (FIG. 1) has a static latch, a static latch representing the simplest form of a bistable circuit and being constructed from two cross-coupled inverters. The first inverter has an n-channel transistor M1 and a p-channel transistor M3. The second inverter of the memory cell has an n-channel transistor M2 and a p-channel transistor M4. What is achieved by the cross-coupling of the inverters is that the output of one inverter controls the input of the other inverter. The two CMOS inverters are electrically connected to complementary bit lines BL and BLQ via two NMOS selection transistors M5 and M6. The use of complementary bit lines BL and BLQ increases the reliability and reduces the sensitivity toward fluctuations of the device characteristic parameters. The gate terminals of the selection transistors M5 and M6 are in each case electrically connected to a first word line WL1. The selection transistor M5 is connected to a first memory node K1 of the memory cell and the selection transistor M6 is connected to a second memory node K2 of the memory cell. The SRAM memory cell illustrated in FIG. 1 is referred to as a 6T memory cell. Because of the “active load elements” M3 and M4, this cell type requires only relatively short times for reading or writing data. A further embodiment (not illustrated) of an SRAM memory cell is the 4T SRAM memory cell, in which the transistors M3 and M4 are replaced by passive load elements. The proposed concept can also be used for other types of memory cells.
The method of operation of the memory cell having active load elements in accordance with FIG. 1 is explained on the basis of the voltage profiles—shown in FIG. 2—of signals that flow through the first word line WL1 and the bit line pair BL and BLQ. External signals are represented by trapezoidal shapes in FIG. 2, while the generally weaker signals of the memory cell have been depicted with more realistic rise and fall times. It is assumed, by way of example, that a first logic state “1” is defined by a high potential on the left-hand side of the memory cell in the memory node K1. It follows from this that the transistor M1 turns off in this state. A write or read operation is initiated by the transistors M5 and M6 being activated under the control of the first word line WL1. A write operation is carried out by drivers pulling the signal on the bit line BL and by pulling the signal on the bit line BLQ that is complementary thereto to logic levels “0” and “1”, respectively. In order to write a first logic state “1” to the memory cell, it is necessary, according to the definition assumed above, for the complementary bit line BLQ to have a logic state “0”.
Generally, it can be stated that that memory node (K1 or K2) of the memory cell which is intended to be brought to a low potential has to be brought to a voltage less than the switching threshold of the opposite inverter from outside the memory cell. The other node is intended to lie above a voltage threshold.
For the above mentioned writing in of a logic state “1”, i.e. to overwrite a stored logic state “0”, this means that the memory node K2 has to be brought to a potential less than the switching threshold of the opposite inverter. During the write operation, the transistors M6 and M4 form a voltage divider, which has to be dimensioned in accordance with the above specification. The resistance of the transistor M4 must be several times greater than the resistance formed by the transistor M6. Thus, during the write operation, the transistor M1 is turned off and the memory node K1 is pulled to a higher voltage potential by the transistors M5 and M3. When memory node K1 is pulled to a higher voltage potential, the transistor M2 is turned on. The first word line WL1 can then be switched off again since the desired state has been written to the cell.
In order to read out the logic state “1”, first the bit lines BL and BLQ are precharged to a precharge voltage. The precharge voltage is chosen in such a way that the cell is not written to unintentionally according to mechanisms described previously. Choosing the precharge voltage in such a way that the cell is not written to unintentionally is referred to as nondestructive reading. In the event of access to the memory cell, a current flows via the transistors M5 and M3 and also M6 and M2, depending on the precharge voltage. In order that the memory state of the memory cell is not changed, however, the memory node K2 has to be brought to a potential less than the switching threshold of the opposite inverter. It follows from this that the resistance formed by the transistor M6 must be approximately three times as large as that of the transistor M2. The writing and reading of the logic state “0” to and from the memory cell are effected in a corresponding manner.
Generally, an operation of writing a logic state to the memory cell may be described as follows. The bit line pair BL and BLQ is precharged to a high potential (as an alternative, said bit lines can also be precharged to a low potential or to an arbitrary reference voltage). If the word line is selected, the selection transistors connected to the memory cell are switched on. One of the memory nodes of the memory cell has a memory state “0” and the other memory node has a memory state “1”. The memory node which has the low memory state “0” pulls the bit line connected to said memory node to a low potential (logic state “0”). A sense amplifier (not illustrated) accelerates the read-out and amplifies the fall of the signal on the bit line connected to the voltage node having the memory state “0” from the state with a high potential to the state with a low potential and simultaneously holds the high potential state on the second bit line. The sense amplifier starts to operate or read out a state only when a specific voltage difference occurs between the two bit lines BL and BLQ. In addition to the voltage amplification described, the current of the memory cell can also be directly amplified.
An operation of writing a memory state to a memory cell can generally be carried out as follows. One of the bit lines is precharged to a high potential and the other bit line of the bit line pair is precharged to a low potential. If the memory cell to which a memory state is intended to be written is selected via a word line and if the memory states in the two memory nodes of the memory cell correspond to the potential states on the bit lines to which the respective memory node of the memory cell is connected, then the memory states in the two memory nodes remain unchanged. However, if the memory nodes have memory states which are different from the potentials of the bit lines to which a respective one of the memory nodes is connected, the memory states in the memory nodes are changed. That memory node which has stored a logic memory state “1” (high potential) is thereby pulled to a logic memory state “0” (low potential). In a corresponding manner, the state of the other memory node is set from a logic memory state “0” (low potential) to a logic memory state “1” (high potential).
One disadvantage in the case of semiconductor memory cells, in particular in the case of the SRAM memory cells, is the problem area that leakage currents flow into the memory cell, in particular when the memory cell of a memory cell array is connected to a plurality of memory cells in the non-selected state. One possibility for keeping the leakage current as low as possible is afforded by choosing the threshold voltage of the transistors of the memory cell to be relatively high. However, this in turn results in the disadvantage that the reading or writing of a memory state from or to the memory cell proceeds more slowly and the sequence of a memory operation is significantly impaired.
As depicted in FIG. 3, a multiplicity of memory cells Z0 to Zn are usually connected to a bit line pair BL and BLQ. If the memory state of the memory cell Z0 is read out, a current iC flows into the cell in the exemplary embodiment illustrated. The current on the bit line BLQ therefore decreases and has the value I-ic. At the same time, leakage currents iL1 to iLN flow from the bit line BL into the corresponding cells Z1 to ZN which are in each case in the non-selected state. This results in an overall leakage current iL, whereby a current I-iL flows from the bit line BL into a current evaluation circuit SBS. The current difference between the two bit lines BL and BLQ is determined by means of this current evaluation circuit SBS or “sense amplifier”. The current evaluation circuits SBS use the current signals I-iC and I-iL directly to determine the memory state in the memory cell to be read. Voltage sense amplifiers, by contrast, use the voltage difference between the two bit lines that is generated when reading from the selected memory cell between the two bit lines BL and BLQ. Both the current evaluation circuit SBS and a voltage sense amplifier circuit evaluate a memory state read out from a memory cell only when a certain voltage difference ΔV or a certain current difference ΔI occurs between the two bit lines. As illustrated in FIG. 4, the memory state of the memory cell Z0 can be evaluated by the current evaluation circuit SBS (FIG. 3) only when a current difference greater than or equal to ΔI occurs between the bit lines BL and BLQ. If no leakage current iL1 to iLN flowed into the non-selected memory cells Z1 to ZN in FIG. 3, then the current on the bit line BL would have a constant value I.
As a result of the read-out of the memory cell Z0, the current iC flows into the memory cell Z0 and the current on the bit line BLQ falls over time in accordance with the upper illustration in FIG. 4. The current difference ΔI between the bit lines BL and BLQ that is required for read-out by the current evaluation circuit SBS (FIG. 3) is therefore reached at the instant t1. However, since leakage currents in each case flow into the non-selected memory cells Z1 to ZN, as already mentioned, the current on the bit line BL is reduced to the constant value I-iL. As a result, as illustrated in the lower current curve profile in FIG. 4, the current difference ΔI between the bit lines BL and BLQ is not reached until at a later instant t2. As a result of the total leakage current iL, the read-out of a memory state is significantly prolonged. The instant at which the read-out begins is delayed by t2−t1. Depending on how many memory cells are arranged between the bit lines BL and BLQ, and on the magnitude of the leakage currents that in each case flow into the non-selected memory states, in extreme cases there may even be the consequence that the overall leakage current iL is just as large as the current I which originally flows through the lines BL and BLQ. In such a state, it is no longer possible to read out a memory state of a selected memory cell since the current difference ΔI required for the read-out cannot be reached. Therefore, it is particularly important to minimize the leakage currents or avoid them in such a way that they no longer have any influence for the assessment or the writing-in of a memory state and do not delay a write/read operation.
U.S. Pat. No. 6,181,608 B1 discloses a 6T SRAM memory cell and a method for reading from this memory cell by means of which the problem area of leakage current may be prevented. For this purpose, the SRAM memory cell has selection transistors having a lower threshold voltage than the transistors of the two inverters of the SRAM memory cell. Furthermore, the integrated circuit in which the SRAM memory cells are arranged has a control circuit for controlling the voltages of the word lines. Said control circuit is connected to all the word lines of the integrated circuit. The signals on the word lines are set by said control circuit in such a way that the leakage current that flows into the non-selected memory cells is intended to be minimized. For this purpose, the gate terminals of the selection transistors of the non-selected memory cells are not connected to ground potential VSS. Rather, the gate terminals of the selection transistors are “underdriven” by virtue of the control circuit applying a negative voltage in the range of a few to a few hundred millivolts to the word lines connected to the non-selected memory cells. A disadvantage of this circuit arrangement is that, on the one hand, a relatively costly and complex circuit structure is necessary for controlling said word lines and the signals thereof and, on the other hand, the “underdriving” of the word lines connected to the non-selected memory cells is relatively difficult and can only be carried out very inaccurately. As a result, the leakage currents that flow into the individual non-selected memory cells cannot be eliminated and significantly influence the reading from or writing to the memory cell.
Furthermore, Agawa, K. et al.: “A Bit-Line Leakage Compensation Scheme for Low-Voltage SRAMs” in Digest of Technical Papers, Symposium on VLSI Circuits, pp. 70-71, June 2000, discloses a circuit arrangement for compensation of a bit line leakage current. The leakage current flowing into the non-selected memory cells from a bit line is detected during a precharge cycle and compensated for by an additional circuit arrangement in the integrated circuit during a write/read operation. The leakage current compensation circuit is electrically connected to the two bit lines of a bit line pair and arranged between the memory cells and the current evaluation circuit connected downstream. The leakage current compensation circuit has two p-channel transistors arranged symmetrically between the bit lines of the bit line pair, a respective one of these two p-channel transistors being used to detect the leakage current on that bit line to which the respective p-channel transistor is connected. Furthermore, the leakage current compensation circuit has two other p-channel transistors that are also formed in a symmetrical arrangement between the bit lines of the bit line pair. By means of these two additional p-channel transistors, a current having the same magnitude as the detected leakage current is passed onto the respective bit line in order to compensate for the detected leakage current. This compensation by means of the two additional p-channel transistors is effected during a write/read operation of a memory cell of the memory cell array. The four p-channel transistors are controlled in such a way that the detected leakage current is stored in a capacitance of the leakage current compensation circuit and the stored leakage current flows onto the bit line by means of an activation signal for activating the second p-channel transistors. The leakage current is thus firstly converted into a voltage and stored in a capacitance of the leakage current compensation circuit. A compensation current is generated therefrom and is applied to the corresponding bit line for compensation of the leakage current. This circuit arrangement for leakage current compensation is very costly and very complex in its construction. A further disadvantage of this arrangement is the large capacitance required to store the leakage current. Furthermore, this circuit arrangement only detects the total leakage current, that is to say the sum of all those leakage currents which flow into the non-selected memory cells of the memory cell array. This compensation circuit does not make it possible to compensate for the leakage current separately in each individual memory cell into which a specific leakage current flows.
Kawaguchi, H. et al.: “Dynamic Leakage Cut-off Scheme for Low-Voltage SRAMs” in Digest of Technical Papers, Symposium on VLSI Circuits, pp. 140-141, June 1998, discloses a circuit arrangement for leakage current reduction in which the bias voltages of the n-type and p-type well regions in the substrate are changed dynamically to supply voltage potential VDD and ground potential VSS, respectively, to the selected memory cell, while the bias voltages of the well regions of the non-selected memory cells are held at the respective voltage potential (for the n-type well region approximately 2×VDD and for the p-type well region approximately −VDD). As a result, the threshold voltage of the selected memory cell becomes relatively low and the threshold voltage of the non-selected memory cells becomes relatively high. A significant disadvantage of this circuit arrangement is that the bias voltage coefficient of the substrate is significantly reduced as a result of the dynamic variation of the substrate voltage and constitutes a decisive disadvantage particularly in the case of recent technologies.
Therefore, it is an object of the invention to provide a circuit and a method by means of which the leakage current can be compensated for in a simple manner and with a low outlay and whereby the time duration for a write/read operation is only minimally prolonged.